Clock rates in electronic devices may determine the rate at which digital bits may be processed. A faster clock rate may enable more digital bits to be processed by an electronic device. Multiplying-delay-locked-loops (MDLLs) are often used to upconvert clocks from slower clocks by multiplying the slower clock by a predetermined scaling factor. For example, a reference clock operating at 10 MHz has a 100 ns period. If a faster clock uses scaling factor of eight, or 8×, it is desirable to have the faster clock operate at 80 MHz having a period of 12.5 ns so that eight faster clock cycles will synchronize with one reference clock cycle.
FIG. 1 shows an exemplary multiplying-delay-locked-loop circuit using a counter 13 and multiplexer (MUX) 11 with a delay line 12 to scale the upconverted clock signal 14 to the reference clock signal 10. The MUX 11 may select an input signal from one of its inputs to propagate further into the MDLL—a reference clock from input 10 or an output clock from terminal 14. The delay lines 12 may impose delay on propagation of its input signal in an amount determined by an input control signal. The delay line 12 may include a plurality of delay elements which, if selected, delays the input signal by a predetermined amount. The counter 13 may increment on each rising (or falling) edge of the output clock signal 14 and may generate a STOP output when the count value reaches a threshold count value representing the scaling factor applied by the MDLL. For example, for a 10× clock, the count value may be set to 10; the MUX 11 may be selected to recirculate an output of the delay line 12 back to the delay line 12 until the tenth cycle when the counter 13 asserts the STOP signal line. Thereafter, the MUX 11 may be switched to the reference clock input 10 and operation ceases until a new clock edge appears in the reference clock signal. In this manner, the MDLL generates a high speed clock having a predetermined number of clock cycles for each clock cycle of a reference clock.
Ideally, given a scaling factor of N, edges within the reference clock would coincide perfectly with an edge of a clock signal output at terminal 14. Such coincidence does not always occur, for example, if the delays imposed by the delay line 12 are not tuned appropriately for the clock scaling factor. If, for example, the delay line 12 does not impose sufficient delay on the recycled clock cycle that is outputted from the delay line 12, passed through MUX 11, and inputted back to the delay line 12, the counter 13 will reach its threshold count value before a new edge of the reference clock is received. In such a case, the MDLL waits in a dormant state until the reference clock edge is received, whereupon it resumes operation. By contrast, if the delay line 12 imposes too much delay, the counter 13 will not reach its threshold count value by the time the next edge appears in the reference clock signal. Both conditions introduce error in the MDLL's performance. Moreover, the amount of delay imposed by a delay line 12 can change based upon temperature, process, and operating voltage present in the integrated circuits in which the MDLL is operating. Thus, existing MDLLs include control systems (not shown in FIG. 1) to reconfigure the delay imposed by the delay line 12 and tune the MDLL to minimize such errors.
Known control systems detect a phase difference between the reference clock edge and a corresponding edge in the output clock and adjust an amount of delay imposed by the delay line 12 based on the detected difference. For example, the control block may increment or decrement a number of delay elements of the delay line 12 depending on whether the multiple upconverted clock cycles lag or lead the corresponding reference clock cycle. Another control block example may adjust the delay through each of a fixed number of delay elements.
The problem with these existing systems is that the delay line is reconfigured once per clock cycle of the reference clock. In an MDLL where N represents the upconversion factor of N (e.g. N=10 for a 10× clock) and Δt represents the smallest adjustable increment of delay supported by the delay line, the conventional systems adjust delay by a factor of 2*N*Δt. This may be too coarse a granularity to provide appropriate control of the MDLL.
FIG. 2 illustrates this problem. FIG. 2 shows a reference clock signal cycle 21 and the upconverted clock signals 22 and 23 corresponding to a first and second reference clock cycle respectively. In this example, the upconverted clock may be configured to be 4 times the reference clock, with ideally four fast clock cycles synchronized with one reference clock cycle.
During the first reference clock cycle, the control block may select a first set of delay elements resulting in the upconverted clock having a cycle period of 2D, so the time it takes to complete half a cycle is D. After complete four clock cycles, a total time of 8D, (2D per clock cycle times 4 clock cycles) will have elapsed. However, in this example, the reference clock cycle takes longer than time 8D to complete, resulting in a synchronization discrepancy 24 between the upconverted clock signal 22 and the reference clock signal 21. To reduce the discrepancy, the control block may add another delay element to each upconverted clock cycle 23 in the next reference clock cycle. This may increase the time to complete each upconverted clock cycle by 2x, and each half clock cycle by x. In this case, the total time to complete the four upconverted clock cycles will be 8*(D+x).
However, by adding the additional time 2x to each upconverted clock cycle, the time required to complete the four upconverted clock cycles may now take longer than the time to complete a reference clock cycle, resulting in another synchronization discrepancy 25. In this case, the control block may remove the delay element that it previously added, and the process may to continue to iterate in this fashion, switching between adding and removing delay elements in each reference clock cycle.
Thus, the ability of these existing systems to reconcile upconverted clock cycle times with a reference clock cycle time is limited, since the existing systems must change each upconverted clock cycle time within a reference cycle by the same minimum amount. In systems with large scaling factors resulting a large number of upconverted clock cycles corresponding to a reference clock cycle, these minimum amounts can add up quickly and further limit the ability of the control block to reconcile multiple upconverted clock cycles with the corresponding reference clock cycle.
There is a need for improved delay control where upconverted clock cycle periods may be adjusted with improved resolution to better reconcile multiple upconverted clock cycles with the corresponding reference cycle.